Logic devices such as FPGAs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of EDA tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, placement, and routing. Even with the assistance of EDA tools, timing requirements for the system design may still not be satisfied after several iterations of the CAD flow.
The speed of the circuitry in a system is determined in part by the length of the wires between registers and the number of circuit elements a signal has to travel between registers. Generally, it is desirable to minimize these conditions. Various tools and procedures are available to assist in the design process to improve timing of the system including register transfer language (RTL) timing viewers, statistical static timing analysis (SSTA) based timing estimates, and other techniques.
However, even with these tools and procedures, designers still have difficulty determining reasonable performance expectations given a current implementation of a system design on a target device. In addition, identifying parts of the system design that should have placement constrained and parts of the hardware description language that need to be changed in order to improve performance remain a challenge.